1. Field of the Invention
The present invention relates to a printed wiring board and a method of manufacturing the printed wiring board.
2. Discussion of the Background
A build-up printed wiring board is a type of a printed wiring board (hereinafter referred to as “PWB”) that has insulation material filled between conductive circuits. Japanese Patent Laid-Open Publications H11-176985 and H11-243279 describe build-up PWBs in which conductive circuits and interlayer insulation resin layers are alternately laminated, and the conductive circuits provided on lower and upper layers are electrically connected through via-holes. In these PWBs, spaces between the wiring patterns forming conductive circuits are filled with dielectric interlayer insulation layers. The conductive circuits have cross sections that are substantially rectangular, and thus side faces of the conductive circuits are substantially parallel to one another. The contents of the above publications are incorporated herein by reference in their entirety.
Also, Japanese Patent Laid-Open Publication H06-57453 describes an etching process. In this process, a substrate having a metal layer formed on its base material is prepared; an etching resist is formed on the substrate; a resist-pattern is formed by exposing to light and developing the resist layer; the metal layer portion in the area where the etching resist is not formed is dissolved and removed; the etching resist is exfoliated; and the metal layer under the resist becomes a conductive circuit with a prescribed pattern. That is, using a subtractive method or a tenting method, conductive circuit is formed after etching away the metal layer exposed in the area where the etching resist is not formed. However, resultant conductive circuits tend to have a smaller cross-section, since the metal layer is etched both in vertical and horizontal directions on the substrate surface. Accordingly, compared with the conductive circuits formed using an additive method, conductor resistance values are higher.
ICs have become faster in recent years, and at the same time wiring patterns of PWBs equipped with such ICs have become even more microscopic. Such ICs occasionally experience malfunctions due to crosstalk or delayed signal transmission in a PWB where (L/S) is 15/15 μm or less, when (L) is the smallest conductor width and (S) is the smallest space. Therefore, a PWB which has a smaller (L/S) but reduced crosstalk and delayed signal transmission is desired. Also, a manufacturing method which allows a PWB to have conductive circuits with lower resistance is desired.